1. Field of Invention
This invention relates to a pulse generator, such as used in an LSI tester; and, more particularly, to a pulse generator having a slew rate controller.
2. Description of Prior Art
In the conventional pulse generator, upon receipt of differential signals inputted from differential signal sources, differential amplifiers produce pulse signals of desired levels, and the slew rate of the signal is controlled by a slew rate controller provided at an output stage of the differential amplifier.
FIG. 1 shows an exemplary conventional pulse generator, wherein differential amplifier 2 outputs a pulse signal, of a desired level, upon receipt of a differential signal. Differential amplifier 2 comprises NPN transistors Q5, Q6, current source I4, and resistor R3. A slew rate controller 3 is provided which outputs pulse signals such that the rising time and falling time of the signal outputted from differential amplifier 2 are limited. Slew rate controller 3 comprises NPN transistor Q7, PNP transistor Q8, current sources I5, I6, and capacitors C3, C4.
The operation of the conventional pulse generator will now be described with reference first to the operation of the differential amplifier 2, and then the operation of the slew rate controller 3.
Operation of Differential Amplifier
When the differential signal (see H/L) is at a high level, NPN transistor Q5 is turned ON, and NPN transistor Q6 is turned OFF, so that no current flows through resistor R3. Voltage VH is outputted from amplifier 2. Conversely, when the differential signal is at a low level (L), NPN transistor Q5 is turned OFF, and NPN transistor Q6 is turned ON, so that current Id of current source I4 flows through resistor R3. In other words, the voltage drop across resistor R3, caused by the change in collector current, becomes the amplitude of the pulse signal. Then, the high level of the pulse signal becomes "VH" and the low level of the pulse signal becomes "VH-Rc.times.Id", wherein Rc indicates the resistance value of resistor R3.
Operation of Slew Rate Controller
When the pulse signal, derived from differential amplifier 2, is raised, current flows between the collector of NPN transistor Q7 and the emitter thereof, so that capacitor C3 is charged. At this time, no current flows through the collector of transistor Q8 and the emitter thereof, and capacitor C4 is charged by current supplied from source I6. As a result, the rising time of the output signal from slew rate controller 2 is delayed from the rising time of the pulse signal outputted from amplifier 2.
Thus, when the pulse signal outputted from amplifier 2 falls, no current flows between the collector and emitter of transistor Q7, and current flows from capacitor C3 to source I5, so that capacitor C3 is discharged. At this time, current flows between the collector and emitter of transistor Q7, and current flows from capacitor C4 to transistor Q8, so that capacitor C4 is discharged. Hence, the falling time of the output signal from slew rate controller 3 is delayed from the falling time of the pulse signal outputted from amplifier 2.
Under such conditions, the slew rate can be controlled by controlling the amount of current supplied by sources I5 and I6.
However, there is a problem encountered by prior art devices in that the slew rate controller must have complementary transistors.